Random access memory (RAM) is a component used within electronic systems to store data for use by other components within the system. Dynamic RAM (DRAM) is a type of RAM which uses a capacitor-type storage and requires periodic refreshing in order to maintain the data stored within the DRAM. Static RAM (SRAM) is another type of RAM which retains the information stored within the SRAM as long as power is applied. SRAM does not require periodic refreshing in order to maintain the stored data. Synchronous DRAM (SDRAM) operates within a synchronous memory system such that input and output signals are synchronized to an active edge of a system clock.
RAM is generally organized within the system into addressable blocks, each containing a predetermined number of memory cells. Each memory cell within a RAM represents a bit of information. The memory cells are organized into rows and columns. Each row of memory cells forms a word. Each memory cell within a row is coupled to the same wordline which is used to activate the memory cells within the row. The memory cells within each column of a block of memory are also each coupled to a pair of bitlines. These bitlines are also coupled to local input/output (LIO) lines. These local input/output lines are used to read data from an activated memory array or write data to an activated memory array. The pair of bitlines includes a bitline and an inverse bitline. A memory cell is therefore accessed by activating the appropriate wordline and pair of bitlines.
Memory circuits are fabricated on wafers. Wafer yield is defined as the ratio of non-defective chips to the number of total chips fabricated on a given wafer. In general, as integration density in semiconductor memory devices increases, the likelihood of defective cells in any one memory array also increases. Therefore, the higher the integration density of chips fabricated on a given wafer, the lower the wafer yield.
It has been determined that an effective method for increasing wafer yield is to use redundant memory to replace defective memory. Redundant memory includes redundant memory cells which are configured in rows and/or columns and are used to replace rows and/or columns of the main memory array which are found to have one or more defective memory cells.
A block diagram of a two-array memory circuit with a redundant memory circuit for each main memory array is illustrated in FIG. 1. A first redundant memory circuit 6 is associated with the main memory array 2, while a second redundant memory circuit 8 is associated with the main memory array 4. Each main memory array has a corresponding memory controller 5. The redundant memory circuits 6 and 8 each have a redundancy memory array 1 and 3, respectively, and a redundancy decoder circuit 7 and 9, respectively. The redundancy memory arrays 1 and 3 are groups of redundancy memory cells arranged in rows and/or columns.
Initially, the redundancy memory arrays 1 and 3 have unspecified addresses. After fabrication, the memory cells within the main memory arrays 2 and 4 are tested. The redundant memory rows and/or columns are then used to replace rows and/or columns within the main memory arrays 2 and 4 which are found to include defective memory cells. The redundant decoder circuits 7 and 9 are programmable in such a manner as to match the addresses of rows and/or columns within the main memory arrays 2 and 4 which include defective memory cells. The defective rows and/or columns within the main memory arrays 2 and 4 are then decoupled or disabled, either electrically using the output of the appropriate redundant decoder circuit 7 and 9, or physically with a local fuse.
A more detailed representational block diagram of the organizational structure of a typical main memory array and redundant memory array configuration is illustrated in FIG. 2. As shown, the configuration includes two normal n.times.m main memory arrays 10, wherein n is the number of rows in each array and m is the number of columns. The configuration further includes two redundant memory arrays 50 of n.times.k dimensions, where n is the number of redundancy rows in each redundant memory array and k is the number of redundancy columns.
Initially, the redundancy rows in the redundancy memory arrays 50 have no programmed addresses. Instead, redundancy address decoders 60 are coupled between the redundancy memory arrays 50 and the normal memory arrays 10. When a defective cell is discovered in testing of the memory device, the redundancy address decoders 60 match the addresses of the defective rows to redundancy rows in the redundancy memory arrays 50. After the address of the defective row is mapped to a row within the redundant memory array, the defective row is decoupled or disabled. The more rows available in the redundancy memory array 50, the more rows with defective cells in the normal memory arrays 10 which can be replaced.
In operation, when a memory write or read cycle is executed, access to the defective row within the normal memory array 10 is prevented because the redundant address decoders 60 are responsive only to the addresses of the redundant rows 50. If the write or read cycle involves a defective memory cell, then the redundant address decoders 60 will recognize the address and route the information to or from the proper redundancy row within the redundant memory array 50. If the redundant address decoders 60 do not recognize the address, the read or write operation will be performed as usual, with the information being routed to and from the main memory arrays 10. Normal row address decoders 20 and normal row drivers 40 are used to control the flow of information to and from the normal memory arrays 50.
Alternatively, and as an additional assurance of accuracy, the memory configuration may include an accompanying fuse array 30 wherein a polysilicon fusible link is connected to each row address within the normal main memory array 10. When a defective memory cell is discovered within the normal memory array 10, an available redundancy row within the redundant memory array 50 will be programmed by the redundant address decoder 60, and the defective row within the main memory array 10 is disabled by blowing the polysilicon fusible link to the row address corresponding to the defective row within the normal memory array 10.
The typical configuration of one redundant redundant memory array per normal memory array is often insufficient for replacing all defective cells within the normal memory array. Often, multiple redundant memory arrays will be used per normal memory array in order to increase wafer yield of the memory device. FIG. 3 shows a block diagram of a redundancy memory configuration using two redundant memory circuits 300 per normal memory array 301. The normal memory arrays 301 are each accompanied by a memory controller 304. Each redundant memory circuit 300 includes a redundancy row memory array 302 and a redundancy row address decoder circuit 303. The redundancy row address decoder circuit 303 is used to program the redundancy memory array 302 whenever a defective cell is discovered within the normal memory array 301. As more redundancy memory circuits 300 are used, the wafer yield is increased.
However, in a semiconductor memory with multiple normal memory arrays 301, each additional redundancy memory circuit 300 requires significant space and additional trace layout on the die on which the memory circuit is formed. Furthermore, each redundancy memory circuit 300 requires its own redundant row address decoder 302 and redundancy row driver 303, which also demand additional space and trace layout on the die. These additional costs and space requirements make the typical redundancy memory configuration unappealing. What is needed is an improved redundancy memory configuration which increases wafer yield and requires less die space to implement.